Keil yada destek veren herhangi bir IDE altında kullanılabilir. Seri üretim amaçlı olarak J-Flash programı ile kullanamazsınız.
Low-cost J-Link for educational purpose
J-Link EDU
Low-cost J-Link for educational purpose J-LINK EDU is identical to J-Link BASE and offers the same functionality. It has been designed to allow students and educational facilities as well as hobbyists access to top of the line debug probe technology.
Full J-Link Support
Unlimited Breakpoints
The unlimited breakpoints in flash memory feature can be used free of charge for evaluation. The evaluation period is not time limited. For commercial use a separate license is required.
Free Software Updates
As a legitimate owner of a SEGGER J-Link, you can always download the latest software free of charge. Though not planned and not likely, we reserve the right to change this policy. Note that older models may not be supported by newer versions of the software. Typically, we support older models with new software at least 3 years after end of life.
Supports concurrent access to CPU by multiple applications
J-Link allows multiple applications to access a CPU at the same time. This has numerous applications. J-Link commander can be used in parallel to a debugger, a tool to communicate via DCC can be used in parallel to a debugger or a visualization tool such as Micrium's u/C-Probe or SEGGER's kernel viewer embOSView. This feature is currently not available for Cortex A and R cores.
Crossplatform support
runs on Windows, Linux, Mac OS X. The MAC and Linux versions are fully usable, but limited to the following components:
J-Link Commander, command line GDBServer, shared library (DLL-equivalent)
Limitations
Licensing and Support
J-Link EDU may only be used for non-commercial purposes. J-Link EDU does not include support.
Specifications
| Specification | Value |
|---|---|
| Supported OS | Microsoft Windows 2000, XP, 2003, Vista, 7 and newer Linux Mac OSX 10.5 and higher |
| Electromagnetic compatibility (EMC) | EN 55022, EN 55024 |
| Operating temperature | +5°C ... +60°C |
| Storage temperature | -20°C ... +65 °C |
| Relative humidity (non-condensing) | Max. 90% rH |
| Mechanical | |
| Size (without cables) | 100mm x 53mm x 27mm |
| Weight (without cables) | 70g |
| Available Interfaces | |
| USB interface | USB 2.0 |
| Target interface | JTAG/SWD 20-pin |
| JTAG/SWD Interface, Electrical | |
| Power supply | USB powered Max. 50mA + Target Supply current. |
| Target interface voltage (VIF) | 1.2V ... 5V |
| Current drawn from target voltage sense pin (VTRef) | < 25µA |
| Target supply voltage | 4.5V ... 5V (if powered with 5V on USB) |
| Target supply current | Max. 300mA |
| Reset type | Open drain. Can be pulled low or tristated |
| Reset low level output voltage | VOL <= 10% of VIF |
| For the whole target voltage range (1.2V <= VIF <= 5V) | |
| LOW level input voltage (VIL) | VIL <= 40% of VIF |
| HIGH level input voltage (VIH) | VIH >= 60% of VIF |
| For 1.2V >= VIF <= 3.6V | |
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 10% of VIF |
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 90% of VIF |
| For 3.6 <= VIF <= 5V | |
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF |
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF |
| JTAG/SWD Interface, Timing | |
| JTAG speed | Max. 15 MHz |
| SWO sampling frequency | Max. 7.5 MHz |
| Data input rise time (Trdi) | Trdi <= 20ns |
| Data input fall time (Tfdi) | Tfdi <= 20ns |
| Data output rise time (Trdo) | Trdo <= 10ns |
| Data output fall time (Tfdo) | Tfdo <= 10ns |
| Clock rise time (Trc) | Trc <= 3ns |
| Clock fall time (Tfc) | Trc <= 3ns |